1. Field of the Invention
The present invention relates to logic circuits and particularly to logic circuits in dual rail design.
2. Description of the Related Art
Dual rail circuits are particularly preferred for cryptographical applications, but also for other fast logic applications. Here, for every operand, both the value of the operand itself and the inverted value of the operand are provided and processed. Then, not only the calculated bit but also the inverted value of the calculated bit is obtained at the output side. Thereby, it is ensured that the current consumption is independent of whether the numbers to be processed are logic zeros or logic ones.
A higher security with such dual rail circuits is obtained when an evaluation mode or data mode always follows a preparation mode or precharge mode or predischarge mode. In the precharge mode, both the input and the inverted input are brought to the same high potential. In the predischarge mode, however, both the operand and the inverted operand are brought to the same low potential. Each time, when a data mode follows a precharge mode, it is ensured that always only one line changes from one mode to the next, which means at a transition from a preparation mode to an evaluation mode or data mode. Thereby, a current profile is obtained which is fully independent of the data to be processed.
XOR circuits are used in different situations. One application is in counters, wherein here an XOR-operation of a propagate signal Prop with a carry signal Car of a next-lower bit slice is required. FIG. 2 shows an existing XOR circuit for linking a propagate signal Prop and a carry signal Car to obtain a result. The circuit shown in FIG. 2 is also designed in dual rail technique and comprises four inputs 21, 22, 23, 24 and two outputs 25, 26. For implementing the XOR truth table, as illustrated in FIG. 3, for example, six transistors P1, P2, P3, P4, P5 and P6 are required in the known circuit. The circuit shown in FIG. 2 has as the characteristic that all four inputs 21 to 24 are guided to one gate of a PMOS transistor P1, P2, P3, P4, P5, P6, which means that none of the inputs has to be driven. Thus, for operating the XOR circuit shown in FIG. 2, only a very small driver is required on the side of the input operands.
However, it is a disadvantage of the circuit shown in FIG. 2, that when a precharge is performed, all transistors shown in FIG. 2 are non-conductive. This means that all inner nodes float. Thus, in the precharge state, neither the outputs 25 and 26 of the circuit shown in FIG. 2 nor the inner nodes between the individual transistors are driven.
If the circuit transits to the evaluation phase, it has the disadvantage that only one of the two paths is driven with a logic “1”. With an unfavorable layout, where, for example, parasitic couplings into the precharge phase take place, this can cause an error function of the circuit.
If valid values are assigned to the inputs in the next evaluation phase, again, a Vdd path is connected to the output bit or the inverted output bit. Since residual charge from the previous cycle can be stored at the inner node of the XOR gate, and since residual charge can further also be stored at the output, effects can result, which again cause performance loss, shunt current and lacking operational reliability. Thus, for example, it can happen that a bit driven due to a residual charge present from a previous cycle, first has to fight the residual charge. During this, a shunt current flows and the circuit becomes slower than necessary. This effect can be significantly intensified by coupling capacitances, which can, in an extreme case, even have the effect that the residual charge “wins” and thus the result will be wrong.
DE 197 12 553 A1 discloses a charge recycling difference logic circuit and memory elements comprising this circuit. An nMOS pass transistor logic network comprising four nMOS transistors for implementing the XOR/XNOR function, is coupled to a precharge circuit, which will connect the output nodes when the clock is low, to bring both output nodes to a voltage equal to half of the difference between Vdd and Vss, and to disconnect the two output nodes from each other in the evaluation node, which takes place when the clock is high.